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【应用手册】 AN 606: POS-PHY Level 4 (SPI-4.2) Loopback Reference Design
The packet over SONET/SDH physical layer (POS-PHY) Level 4—Phase 2 (SPI-4.2)
loopback reference design shows how you can transmit and receive data using the
Altera® POS-PHY Level 4 MegaCore® function and the Stratix® IV and Stratix III
development kits. This reference design uses two instances of the POS-PHY Level 4
MegaCore function, the POS-PHY Level 4 transmitter MegaCore function and
receiver MegaCore function. The reference design provides a general platform for you
to control, test, and monitor the POS-PHY Level 4 operations.
This application note describes how to use the loopback interface with the Stratix IV
and Stratix III FPGA development board that is available in the Stratix IV and
Stratix III development kit, and a high-speed mezzanine card (HSMC).
AN 606: POS-PHY Level 4 (SPI-4.2)
Loopback Reference Design

May 2010 AN-606-1.0




The packet over SONET/SDH physical layer (POS-PHY) Level 4―Phase 2 (SPI-4.2)
loopback reference design shows how you can transmit and receive data using the
Altera POS-PHY Level 4 MegaCore function and the Stratix IV and Stratix III
development kits. This reference design uses two instances of the POS-PHY Level 4
MegaCore function, the POS-PHY Level 4 transmitt

关键词： Altera   FPGA   POS-PHY   Stratix IV   Stratix III